amdocl64.dll

Company
Advanced Micro Devices Inc.
Description

AMD Accelerated Parallel Processing OpenCL 2 0 Runtime

Version
21.19.384.0
Architecture
32 bit
Threat Score
0 %
Original size
59876.8 Kb
Download size
22889.1 Kb
MD5
1e75094d69aa51d93fa4607983d933b1
SHA1
af8340126d9641fe58e2790b4638da2eec607df1
SHA256
de9745fecba8eaf12418e1cec234f818177dc11a30d81608dff1f9a7ffe71e4b

	Start Address: 

  error opening file for writing!

 * Complementary error function.

 * Error function encountered in integrating the

 * The maximum error is implementation-defined.

 * The result shall be within 8192 ulps error from the

 * implementation-defined range. The maximum error is

 * range. The maximum error is implementation

 * range. The maximum error is implementation-defined.

 * range. The maximum error is implementationdefined.

 * to +infinity. Used as an error value returned by the built-in

 The start layer index is stored in the second element of cb0

#error This

#error opencl20.h

'##' cannot appear at start of macro expansion

'#pragma fp_contract' can only appear at file scope or at the start of a compound statement

'%0': unable to pass LLVM bit-code files to linker

'%0': unable to use AST files with this tool

'%0': unable to use module files with this tool

*** unknown regexp error code ***

--EOF (start condition 

.error argument must be a string

.error directive invoked in source file

: error: unable to get target for '



 Unable to display object header: header is NULL

A system error occurred.

An error with the ELF object was encountered.

BOrderedAppendEnable             = %s

Bad start of live segment,

 no basic block

Both arms of conditional operator are unable to produce a constant expression

Bounds checks unable to add

CB:OUTPUT0_ENABLE           = %u

CB:OUTPUT1_ENABLE           = %u

CB:OUTPUT2_ENABLE           = %u

CB:OUTPUT3_ENABLE           = %u

CB:OUTPUT4_ENABLE           = %u

CB:OUTPUT5_ENABLE           = %u

CB:OUTPUT6_ENABLE           = %u

CB:OUTPUT7_ENABLE           = %u

Cannot find start ('{{') of expected %0

Cannot find start of regex ('{{') in %0

Cannot optimize for size and vectorize at the same time. Enable vectorization of this loop with '#pragma clang loop vectorize(enable)' when compiling with -Os/-Oz

ClangOCLFE:Error creating the output file stream

Comment must start with //

DB:COVERAGE_TO_MASK_ENABLE  = %u

DB:KILL_ENABLE              = %u

DB:MASK_EXPORT_ENABLE       = %u

DB:STENCIL_OP_VAL_EXPORT_ENABLE   = %u

DB:STENCIL_TEST_VAL_EXPORT_ENABLE = %u

DB:Z_EXPORT_ENABLE       = %u

Do not automatically import modules for error recovery

Do not error on use of NSAllocateCollectable/NSReallocateCollectable

Don't automatically start assembly file with a text section

E001:Generic Compiler Error Message! 

E002:Internal Compiler Error Message!

Emit an error if a C++ static local initializer would need a guard variable

Emit error if a specific declaration is deserialized from PCH,

 for testing

Enable <

feature>

 in module map requires declarations

Enable -Wall

Enable -Wall and -Wextra

Enable -time-passes memory tracking (this may be slow)

Enable 3DNow! Athlon instructions

Enable 3DNow! instructions

Enable AES instructions

Enable ARC-style weak references in Objective-C

Enable AVX instructions

Enable AVX-512 Byte and Word Instructions

Enable AVX-512 Conflict Detection Instructions

Enable AVX-512 Doubleword and Quadword Instructions

Enable AVX-512 Exponential and Reciprocal Instructions

Enable AVX-512 Integer Fused Multiple-Add

Enable AVX-512 PreFetch Instructions

Enable AVX-512 Vector Bit Manipulation Instructions

Enable AVX-512 Vector Length eXtensions

Enable AVX-512 instructions

Enable AVX2 instructions

Enable AltiVec vector initializer syntax

Enable Apple gcc-compatible #pragma pack handling

Enable C++ Extensions for Concepts

Enable C++ Extensions for Concepts.

Enable C++ exceptions

Enable C++14 sized global deallocation functions

Enable CodeView debug information in object files

Enable DAG combiner alias-analysis heuristics

Enable DAG combiner's use of IR alias analysis

Enable DAG combiner's use of TBAA

Enable GCN ops in tablegen

Enable HSAIL Alias Analysis

Enable Hexagon Double Vector eXtensions

Enable Hexagon Vector eXtensions

Enable KernelAddressSanitizer instrumentation

Enable LSR phi elimination

Enable LTO in 'full' mode

Enable Link Options

Enable MAD

Enable MMX instructions

Enable MSA ASE (MIPS only)

Enable Objective-C Ivar layout bitmap print trace

Enable Objective-C exceptions

Enable Objective-C garbage collection

Enable PC tracing in sanitizer coverage

Enable PGO instrumentation. The accepted value is clang,

 llvm,

 or none

Enable PatchPoint Liveness Analysis Pass

Enable Persistent Commit

Enable SC XNACK workaround if IOMMUv2 is being used

Enable SHA instructions

Enable SPIR-V debug output

Enable SSE 4.1 instructions

Enable SSE 4.2 instructions

Enable SSE instructions

Enable SSE2 instructions

Enable SSE3 instructions

Enable SSSE3 instructions

Enable SVR4-style position-independent code (Mips only)

Enable Software Guard Extensions

Enable System z vector language extension

Enable TBM instructions

Enable X87 float instructions

Enable XOP instructions

Enable abort calls when fast instruction selection fails to lower an instruction: 0 disable the abort,

 1 will abort but for args,

 calls and terminators,

 2 will also abort for argument lowering,

 and 3 will never fallback to SelectionDAG.

Enable additional debug output

Enable an experimental vector type legalization through widening rather than promotion.

Enable basic block tracing in sanitizer coverage

Enable c99 style inlining mode

Enable casting unknown expression results to id

Enable cmp instruction tracing in sanitizer coverage

Enable conditional move instructions

Enable control flow integrity (CFI) checks for cross-DSO calls.

Enable cyclic critical path analysis.

Enable dead store elimination in HSAIL machine code

Enable debug output for linker

Enable device-side debug info generation. Disables ptxas optimizations.

Enable dumpping kernel intermediates

Enable early if-conversion on X86

Enable emission of RTTI data

Enable exception handling

Enable expansion of OpenCL step and smoothstep function

Enable expensive instruction combines

Enable experimental features

Enable extended encoding of block type signature

Enable fast-math-flags for DAG nodes

Enable fma for a*b+c.

Enable four-operand fused multiple-add

Enable frequency counters in sanitizer coverage

Enable full Microsoft Visual C++ compatibility

Enable function overloads based on CUDA target attributes

Enable function overloads based on CUDA target attributes.

Enable generating OpenCL kernel argument name metadata

Enable generating access qualifier postfix in OpenCL image type names

Enable generation phase of PGO instrumentation and specify the path of profile data file

Enable hexagon-qdsp6 backward compatibility

Enable if predication of stores during vectorization.

Enable if-conversion during vectorization.

Enable kernel caching functionality.

Enable load clustering.

Enable mad for a*b+c.

Enable mcount instrumentation

Enable merging of globals

Enable migration of setter/getter messages to property-dot syntax

Enable migration to NS_ENUM/NS_OPTIONS macros

Enable migration to add protocol conformance on classes

Enable migration to annotate property with NS_RETURNS_INNER_POINTER

Enable migration to infer NS_DESIGNATED_INITIALIZER for initializer methods

Enable migration to infer instancetype for method result type

Enable migration to modern ObjC

Enable migration to modern ObjC literals

Enable migration to modern ObjC property

Enable migration to modern ObjC readonly property

Enable migration to modern ObjC readwrite property

Enable migration to modern ObjC subscripting

Enable migration to property and method annotations

Enable migration to use NS_NONATOMIC_IOSONLY macro for setting property's 'atomic' attribute

Enable missed optimization remarks from passes whose name match the given regular expression

Enable motion of merged load and store

Enable name string compression

Enable odd single-precision floating point registers

Enable optimization analysis remarks from passes whose name match the given regular expression

Enable optimization remarks from passes whose name match the given regular expression

Enable optimization that may promote 32-bit integers to 64 bit integers

Enable optimizations based on the strict definition of an enum's value range

Enable optimizations based on the strict rules for overwriting polymorphic C++ objects

Enable optimizations that may ignore signed int overflow

Enable optimized register allocation compilation path.

Enable origins tracking in MemorySanitizer

Enable packed carry-less multiplication instructions

Enable parser support for the __unknown_anytype type

 for testing purposes only

Enable protection keys

Enable recompilation from DebugIL.

Enable recovery for specified sanitizers

Enable recovery mode (continue-after-error).

Enable register pressure scheduling.

Enable runtime interleaving until load/store ports are saturated

Enable sample-based profile guided optimizations

Enable sanitizer coverage for indirect calls

Enable sanitizer statistics gathering.

Enable scheduling after register allocation

Enable scheduling for macro fusion.

Enable single precision denormal handling

Enable sinkinig and/cmp into branches.

Enable sized deallocation functions

Enable some traditional CPP emulation

Enable special debugger support behavior

Enable special debugger support for Objective-C subscripting and literals

Enable stack protectors

Enable stack protectors for functions potentially vulnerable to stack smashing

Enable statistics output from program (available with Asserts)

Enable subregister liveness tracking.

Enable support for exception handling

Enable support for the C++ Coroutines TS

Enable symbolic stride memory access versioning

Enable the 'blocks' language feature

Enable the 'modules' language feature

Enable the *frontend*'s 'fast-math' mode. This has no effect on optimizations,

 but provides a preprocessor macro __FAST_MATH__ the same as GCC's -ffast-math flag

Enable the BB vectorization passes

Enable the GlobalsModRef AliasAnalysis outside of the LTO pipeline.

Enable the LoopLoadElimination Pass

Enable the experimental Loop Versioning LICM pass

Enable the fast instruction selector

Enable the global instruction selector

Enable the heavy weight spir verification pass.

Enable the integrated assembler

Enable the light weight spir verification pass.

Enable the live debug variables pass

Enable the loop vectorization passes

Enable the machine combiner pass

Enable the machine instruction scheduling pass.

Enable the new,

 experimental CFL alias analysis

Enable the new,

 experimental CFL alias analysis in CodeGen

Enable the new,

 experimental LoopDistribution Pass

Enable the new,

 experimental LoopInterchange Pass

Enable the new,

 experimental SROA pass

Enable the post-ra machine instruction scheduling pass.

Enable the shrink-wrapping pass

Enable the specified remark

Enable the specified warning

Enable the superword-level parallelism vectorization passes

Enable the use of the block frequency analysis to access PGO heuristics minimizing code growth in cold regions and being more aggressive in hot regions.

Enable the use of the block frequency analysis to access PGO heuristics to minimize code growth in cold regions.

Enable thread-safe initialization of static variables

Enable three-operand fused multiple-add

Enable timing for Kernel build.

Enable trapping for specified sanitizers

Enable trigraphs

Enable unsafe double to float shrinking for math lib calls

Enable use of AA during MI DAG construction

Enable use of TBAA during MI DAG construction

Enable use of a base pointer for complex stack frames

Enable use of builtin functions

Enable use phase of PGO instrumentation and specify the path of profile data file

Enable use-after-destroy detection in MemorySanitizer

Enable validator dump on fail

Enable value profiling

Enable vector load store in HSAIL machine code

Enable vectorization on interleaved memory accesses in a loop

Enable verbose messages in the fast instruction selector

Enable waves optimization when kernel size is greater than this threshold.

Error 

Error - Failure in saving BIF file %s.

Error - Failure in saving HSAIL file %s.

Error - Failure in saving ISA file %s.

Error - option can never match,

 because another positional argument will match an unbounded number of values,

 and this option does not require a value!

Error - this positional option will never be matched,

 because it does not Require a value,

 and a cl::ConsumeAfter option is active!

Error assembling HSAIL text.

Error at end of module block in AST file

Error in 

Error in backend: %0

Error inserting X86 binary into BIF.

Error loading file '

Error opening '

Error opening '%0': %1

Error opening file '

Error opening file '%0': %1

Error opening info-output-file '

Error parsing file '

Error parsing inline asm

Error printing AMD HSA Code Object:

Error reading '%0'

Error reading bitcode file: 

Error reading stdin: %0

Error renaming module

Error while linking :                         Invalid binary (Missing LLVMIR section)

Error while linking : aclLink failed

Error while linking: Could not load SPIR-V

Expected ',

' as start of index list

Expected '{' to start inferred submodule

Expected '{' to start module '%0'

Expecting %0 '%1' to be held at start of each loop

Export compr instruction has invalid enable mask 0x%x

FIX-IT detected an error it cannot fix

FIX-IT unable to apply suggested code changes

FIX-IT unable to apply suggested code changes in a macro

Fatal error - scanner input buffer overflow

Frame #,

 Start Clock,

 End Clock,

 Time (us) [Frequency: %llu],

 

Generate an indirect jump to enable jumps further than 64M

Generate coverage mapping to enable code coverage analysis

Generic error occurred while handling a record

HTML end tag does not match any start tag

HTML start tag '%0' closed by '%1'

HTML start tag prematurely ended,

 expected attribute name or '>

'

Internal error while dispatching %s: requested ASIC %s,

 backend %d,

 function not implemented for this backend

Internal error while dispatching %s: requested ASIC %s,

 backend %d,

 limit is %d

Invalid OpenCL conversion between %0 and %1 will become an error in future revisions

Invalid error code.

Invalid token at start of a preprocessor expression

LLVM/SPIR-V translation enable mem2reg

List item of type %0 is not valid for specified reduction operation: unable to provide default initialization value

Method type specifier must start with '-' or '+'

Missing '[' at start of message send expression

OpenCL only. Enable less precise MAD instructions to be generated.

Parse error reading diagnostics

Position arguments in format strings start counting at 1 (not 0)

Queue Call,

 CmdBuffer Index,

 CmdBuffer Call,

 Start Clock,

 End Clock,

 Time (us) [Frequency: %llu],

 Pipeline,

 VS/CS,

 HS,

 DS,

 GS,

 PS,

 Verts/ThreadGroups,

 Instances,

 Comments,

 

Runtime pointer checks needed. Enable vectorization of this loop with '#pragma clang loop vectorize(enable)' when compiling with -Os/-Oz

Sp3 internal error: sq_uc.arch is malformed,

 unable to find operand information for encoding 0x%x,

 subencoding 0x%x with specific flags.

Start 

Start of file scope inline assembly

Start timing major build components.....

To enable the generation of 32-bit gpu isa code (default)

To enable the generation of 64-bit gpu isa code (default is 32-bit)

Unable to allocate memory for GOT!

Unable to allocate memory for common symbols!

Unable to allocate section memory!

Unable to calculate the loop count due to complex control flow

Unable to change standard output to binary

Unable to convert application name to UTF-16

Unable to convert command-line to UTF-16

Unable to convert environment variable to UTF-16

Unable to create block named '

Unable to create target: '%0'

Unable to emit indirect symbol attribute for: 

Unable to emit symbol attribute

Unable to evaluate offset for variable '

Unable to evaluate offset to undefined symbol '

Unable to execute command: %0

Unable to find %0 directory,

 expected to be in '%1'

Unable to find plugin '%0'

Unable to find target for this triple (no targets are registered)

Unable to fully unroll loop as directed by unroll pragma because unrolled size is too large.

Unable to fully unroll loop as directed by unroll(full) pragma because loop has a runtime trip count.

Unable to handle compilation,

 expected exactly one compiler job in '%0'

Unable to interface with target machine

Unable to load PCH file

Unable to load plugin '%0': '%1'

Unable to lookup expression

Unable to lookup field reference!

Unable to make temporary file: %0

Unable to merge a subprocess's serialized diagnostics

Unable to open CC_LOG_DIAGNOSTICS file: %0 (using stderr)

Unable to open CC_PRINT_HEADERS file: %0 (using stderr)

Unable to open CC_PRINT_OPTIONS file: %0

Unable to open file %0 for serializing diagnostics (%1)

Unable to open output file '%0': '%1'

Unable to parse rewrite map '

Unable to read PCH file %0: '%1'

Unable to read rewrite map '

Unable to remove file: %0

Unable to rename temporary '%0' to output file '%1': '%2'

Unable to resolve declare reduction construct for type %0

Unable to set memory limit

Unable to transforn 

Unable to unroll loop as directed by unroll(enable) pragma because unrolled size is too large.

Unable to unroll loop the number of times directed by unroll_count pragma because the loop contains a convergent instruction,

 and so must have an unroll count that divides the loop trip multiple of 

Unable to unroll loop the number of times directed by unroll_count pragma because unrolled size is too large.

Unable to write NOP sequence of 

Unable to write nop sequence of 

Undefined behavior: va_start called in a non-varargs function

Unexpected token at start of statement

Unknown error occured.

Use +feature to enable a feature,

 or -feature to disable it.

Used type %0 where floating point type is not allowed,

 this will be an error in a future release

VGIC:ENABLE               = %u

Last update: 21/01/2025